In recent years, a CPU provided with a function that can change a clock frequency by software control for the purpose of reducing power consumption is known. A method of software controlling the Enhanced Intel SpeedStep Technology (EIST) that is an example of the function of changing the clock frequency is disclosed, for example, in Venkatesh Pallipadi “Enhanced Intel SpeedStep Technology and Demand-Based Switching on Linux”
(http://softwarecommunity.intel.com/articles/eng/1611.htm, Jan. 1, 2005). The EIST is installed, for example, in PentiumM (registered trademark: Pentium) that is a CPU produced by Intel Corporation. The fact that a time required for changing the clock frequency is about 10 microseconds and there are six possible combinations of clock and voltage; (1.6 GHz, 1.484 V), (1.4 GHz, 1.420 V), (1.2 GHz, 1.276V), (1.0 GHz, 1.164 V), (800 MHz, 1.036 V) and (600 MHz, 0.956 V) is described in Table1.1 (for example, “Enhanced Intel SpeedStep Technology for Pentium M Processor”(http://softwarecommunity.intel.com/articles/eng/1611.htm, March, 2004).
In recent years, a CPU that can count CPU internal events related to performance is known, for example described in Japanese Patent Publication JP-2000-148475. A wide variety of events is known, and six events; “Unhalted Core Cycles”, “Unhalted Reference Cycles”, “Instruction Retired”, “LLC Reference”, “LLC Misses”, “Branch Instruction Retired” and “Branch Misses Retired” are described in the Section A.4 of the above-mentioned document. Besides, many events can be counted. Moreover, a fact that it is not easy to measure performance of a CPU having a complicated execution configuration such as out-of-order execution is described, for example, in “Performance Counter of Intel Core Micro Architecture·Processor”
(http://jp.xlsoft.com/documents/intel/seminar/4_Core2_perf_counters_J.pdf, 2007).
In a conventional case where the CPU performance strongly depends on retire (execution completion) of instructions, it is sufficient to count a small number of events. In recent years, however, the CPU performance does not depend on the number of retires but strongly on “stall cycles” due to numerous factors. The “stall cycle”, which is a cycle in which there are instructions that should be executed but cannot be executed, is different from an idle cycle having no instruction to be executed.
Moreover, a method of changing the clock frequency of the CPU in accordance with a load state of the CPU, a remaining capacity of a battery and a heat temperature of the CPU is disclosed, for example, in Japanese Patent Publication JP-H09-237132A. Japanese Patent Publication JP-H09-237132A discloses a technique that detects the load state of the CPU by recognizing the number of times of the idle state based on the number of setting a flag indicative of a busy state that is set every time the CPU accesses an I/O (Input/Output) or a memory.
A method of increasing or decreasing a value of a performance index in a range of an electric power consumption index specified by a user is disclosed, for example, in Japanese Patent Publication JP-H11-353052A. The typical performance index in the method described in Japanese Patent Publication JP-H11-353052A is the number of user mode instructions that are executed. Although the number of instructions strongly depends on the clock frequency of the CPU, they do not always have a proportional relationship. Therefore, the clock frequency is determined by measuring the value of the performance index before and after the change in the clock frequency and then considering whether or not a change rate exceeds a predetermined threshold value. On the other hand, a total number of executed instructions is used as the electric power consumption index.
Also, a method of executing the version-up and installation of software at a higher clock frequency as compared with a usual case is disclosed, for example, in Japanese Patent Publication JP-2000-148475A. A computer installed in a mobile body such as a car and the like is often operated at a performance lower than the highest performance or the highest clock frequency of a hardware, in consideration of change in a temperature, continuous battery drive and the interference with other devices. However, when the frequent change in the software in recent years is taken into consideration, this is practically inconvenient unless high speed processing is not carried out at the time of the version-up or installation.
Moreover, a method of operating the CPU at its highest performance or highest clock in a period of system start-up processing is disclosed, for example, in Japanese Patent Publication JP-2001-5661A. The method disclosed in Japanese Patent Publication JP-2001-5661A considers to lower the clock frequency of the CPU to execute an user application in order to reduce the power consumption. This is a method that prevents the system from being re-started at a relatively low speed at a clock less than the highest speed of the CPU, when the system is shut down or standby.
A method of dynamically changing the clock frequency of the CPU when carrying out a process of an I/O bound is disclosed, for example, in Japanese Patent Publication JP-2003-196083A. In the method disclosed in Japanese Patent Publication JP-2003-196083A, a clock is specified for each page that is a unit of a memory management. Instruction codes recorded in the page is executed at the specified clock. The clock is specified in a stepwise manner. For example, the clock frequency is specified in such a way that an OS kernel is executed at a high speed, an input/output waiting function of the OS kernel is executed at a low speed, and an application program is executed at an intermediate speed.
A method of controlling a clock so as to optimize the performance of a device without exceeding the electric power/heat budget of a system is disclosed, for example, in Japanese Patent Publication JP-2005-71365A. The method disclosed in Japanese Patent Publication JP-2005-71365A uses a relative load on a plurality of devices generated by the execution of an application program, mainly a memory device and an I/O device. When the application program accesses the memory device in many times, the clock frequency of the memory device is set relatively higher. On the other hand, when the application program accesses the I/O device in many times, the clock frequency of the I/O device is set relatively higher.
A method of changing the clock frequency of the CPU depending on a batch processing or an interactive processing is disclosed, for example, in Japanese Patent Publication JP-2006-302306A. According to the method disclosed in Japanese Patent Publication JP-2006-302306A, when the batch processing that is rate-limited by the CPU is executed, the clock frequency is set higher. When the interactive processing that is not rate-limited by the CPU such as a word processor is executed, the clock frequency is set lower. However, it is difficult that a user effectively controls the balance between the CPU performance and the system power consumption. Therefore, a graphic interface for adjusting the clock frequency is provided.
A computer system that stops the clock based on an update frequency of a register and whether or not a process is caused by interruption is disclosed, for example, in Japanese Patent Publication JP-H11-110063A. What is assumed in the computer system disclosed in Japanese Patent Publication JP-H11-110063A is a system in which most of the processing requests from the outside are generated by the interruption, and the interruption processing is required to be carried out at a high speed. Whereas, the processing of a key input wait and a completion wait of an I/O device need not be carried out at a high speed. In the wait states, when they are considered to be in the states of a software loop, a HALT instruction execution and the like, writing to the register is not generated at this time.
As described above, in the cases of the conventional techniques, the clock frequency of the CPU cannot be determined based on the stall cycles. In the cases of Japanese Patent Publication JP-2003-196083A and Japanese Patent Publication JP-2005-71365A, the clock frequency is decreased only for I/O in which the idle cycle is evidently generated. Similarly, even if the idle cycles of the I/O processing are considered as the CPU load as described in Japanese Patent Publication JP-H09-237132A, the stall cycles cannot be taken into consideration. In the cases of Japanese Patent Publication JP-2000-148475A, Japanese Patent Publication JP-2001-5661A and Japanese Patent Publication JP-2006-302306A, the clock frequency is increased only in the particular processing specified beforehand such as the version-up, the system start, the batch processing and the like. However, the stall cycles generated by them are not taken into consideration. In the case of Japanese Patent Publication JP-H11-353052A, although the clock frequency of the CPU is changed based on the number of retired instructions, the stall cycles cannot be taken into consideration. The reason is that the stall cycle is not always short even when the number of instructions is large, because the number of cycles required for the execution is different depending on the instruction. That is, when a quotient of the number of cycles other than the stall cycles and the number of total cycles is assumed to an execution efficiency of the instructions, the dependency of the execution efficiency on the number of retired instructions is different depending on the case. Moreover, in the case of the computer system described in the patent document 8, the clock of the CPU is stopped based on the update frequency of the register. Although there is correlation between the update frequency of the register and the stall cycles, the absolute values of the stall cycles are not referred to. Thus, to what extent the clock is to be reduced cannot be determined quantitatively. To determine whether or not to stop the clock is merely disclosed.